December 2010

Programmable logic controller hardware

By Dr. Kelvin T. Erickson

Editor's Note: This is the second part of a two-part article on the main distinguishing characteristics of the PLC. The first part, which ran in the Nov/Dec 2010 InTech (www.isa.org/InTech/basics_201012_2) described the basic hardware and software architecture. This part will cover the scanning of the program and input/output modules.

Scan of I/O and program

The PLC processor has four major tasks executed repeatedly in the following order:

  1. Read the physical inputs.
  1. Scan the ladder logic program.
  1. Write the physical outputs.
  1. Housekeeping tasks.

The processor repeats these tasks as long as it is running. The housekeeping tasks include communication with external devices and hardware diagnostics.

The time required to complete these four tasks is defined as the scan time and is typically ranges from a few milliseconds up to a few hundred milliseconds, depending on the length of the program. For very large programs, the scan time can be relatively long, causing the PLC program to miss transient events, especially if they are shorter than the scan time. In this situation, the possible solutions are:

  1. Break program in program units (tasks, function blocks, or routines) that are executed at a slower rate, and execute the logic to detect the transient event on every scan.
  1. Lengthen the time of the transient event so it is at least twice the maximum scan time.
  1. Place the logic examining the transient in a program unit that is executed at a fixed time interval, smaller than one-half the length of the transient event.
  1. Partition long calculations (for example, array manipulation) into smaller parts so only a portion of the calculation is solved during a scan time.

Depending on the PLC processor, one or more of these solutions may be unavailable.

Normally, during the ladder logic program scan, changes in physical inputs cannot be sensed, nor can physical outputs be changed at the output module terminals. However, some PLC processors have a function block that can read the current state of a physical input and another function block that can immediately set the current state of a physical output. However, using the immediate input/output block incurs a severe time penalty on the program scan. For example, to scan one contact in the ladder logic typically requires less than one microsecond. The time to execute an immediate input/output block typically requires 200 to 300 microseconds. Consequently, these blocks are used sparingly.

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Figure 1: PLC processor scan

From the standpoint of the physical I/O and program execution, the processor scan is shown in Figure 1. The state of the actual physical inputs is copied to a portion of the PLC memory, commonly called the input image table. When the program is scanned, it examines the input image table to read the state of a physical input. When the logic determines the state of a physical output, it writes to a portion of the PLC memory commonly called the output image table. The output image may also be examined during the program scan. To update the physical outputs, the output image table contents are copied to the physical outputs after the program is scanned. In reality, this close coordination between the program scan and the reading/writing of I/O applies only to I/O modules in the same chassis as the processor. For I/O modules in another chassis, there is a communication link or network whose operation is generally not coordinated with the processor program scan. As shown in Figure 2, the communication module scans the remote I/O at its own rate and maintains buffer data blocks. The transfer of data between the processor and the buffer data is coordinated with the program scan. Some PLC processors have no coordination between the program scan and the I/O modules. When an input module channel changes, its status is immediately updated in the input image table and is not coordinated with the start of the program scan.

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Figure 2: Data transfer with remote I/O

Most PLC processors have a watchdog timer that monitors the scan time. If the processor scan time exceeds the watchdog timer time-out value, the processor halts ladder program execution and signals a fault. This type of fault usually indicates the presence of an infinite loop in the ladder program or too many interrupts to the program scan.

The overall execution of the PLC processor scan is controlled by the processor mode. When the PLC processor is in the run mode, the physical inputs, physical outputs, and program are scanned as described previously. When the processor is in program mode (sometimes called stopped), the program is not scanned. Depending on the particular PLC processor, the physical inputs may be copied into the input image, but the physical outputs are disabled. Some processors have a test mode, where the physical inputs and ladder logic are scanned. The output image table is updated, but the physical outputs remain disabled.

Within the processor program, the scan order of the function blocks (www.isa.org/InTech/basics_201012_2) can be specified. Within a function block (or program organization unit), the program written in any of the IEC languages generally proceeds from top to bottom. For ladder logic, the scan starts at the top of the ladder and proceeds to the bottom of the ladder, examining each rung from left to right. Once a rung is examined, it is not examined again until the next ladder scan. The rungs are not examined in reverse order. However, most processors have a jump instruction that one could use to jump back up the ladder and execute previous rungs. However, that use of the instruction is not recommended, because the PLC could be caught in an infinite loop. Even if the processor is caught in an infinite loop, the watchdog timer will cause a processor halt so the problem can be corrected.

Forcing discrete inputs and outputs

One of the unique characteristics of PLCs is their ability to override the status of a physical discrete input or to override the logic driving a physical output coil and force the output to a desired status. This characteristic is very useful for testing. Although there are few exceptions, this override function only applies to physical discrete inputs and physical discrete outputs. In addition, this function is called by different names. Depending on the PLC manufacturer, this function is called input/output forcing, input/output disabling, or override. The forcing function modifies the PLC program scan as shown in Figure 3.

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Figure 3: Relationship of forcing with PLC program scan

For discrete inputs, the force function acts like a mask or a filter. When a physical discrete input is forced, the value in the force table overrides the actual input device status with the value in the force table. An input force/disable/override is often useful for testing a PLC program. If the PLC is not connected to physical I/O, the forces allow one to simulate the inputs. An input force can also be used to temporarily bypass a failed discrete input device so operation may continue while the device is being repaired. However, overriding safety devices in this manner is not recommended.

For discrete outputs, the forcing/disable function acts like a mask. When a particular physical discrete output is forced, the value in the force table overrides the value determined by the result of the logic that drives the output coil. An output force/disable/override is useful for troubleshooting discrete outputs. Forcing an output to the on and/or off state can be used to test that particular output. Otherwise, output forces should not be used. Using an output force to override the PLC logic should be used only temporarily until the logic can be corrected.

ABOUT THE AUTHOR

Dr. Kelvin T. Erickson is a professor of Electrical & Computer Engineering at the Missouri University of Science and Technology (formerly the University of Missouri-Rolla, UMR) in Rolla. His primary areas of interest are in manufacturing automation and process control. He is a registered Professional Engineer (Control Systems) in Missouri. He is a member of ISA and senior member of IEEE.

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