Yorktown Heights, N.Y. – IBM said Monday its researchers have produced the world's smallest working silicon transistor by pushing silicon to limits on a molecular scale not previously achieved.

At six nanometers in length, IBM said the new transistor is at least 10 times smaller than the state-of-the-art transistors in production today. A nanometer (nm) is one billionth of a meter.

To see a detailed schematic produced by IBM, click here.

The Consortium of International Semiconductor Companies in its 2001 International Technology Roadmap for Semiconductors projected that transistors have to be smaller than 9 nanometers by 2016 in order to continue the performance trend. IBM said it is the first company to make working transistors below that gate length.

"The ability to build working transistors at these dimensions could allow us to put 100 times more transistors into a computer chip than is currently possible," said Randy Isaac, vice president of science and technology, IBM Research. "Moreover, this achievement underscores the fundamental challenges of scaling, namely power density, that must be addressed as silicon is pushed to molecular dimensions."

Transistor scaling, or the reduction of the gate length (the size of the switch that turns transistors on and off), improves the performance and speed of chips as well as lowers their manufacturing cost and power consumption per switching event. The information technology industry has been scaling down transistors for the past 30 years to meet demand for smaller and more intelligent electronic devices.

Isaac said scaling to this new molecular level demonstrates the basic transistor concept still functions at this size. Continued innovation will be required to simultaneously achieve high performance and to manage power density and heat dissipation, IBM said. IBM predicted its results would lead to further research into small, high-density silicon devices and allow scientists to introduce new structures and new materials.

IBM researchers made its ultra-thin silicon channel devices and circuits on bonded silicon-on-insulator (SOI) wafers using halo implants and 248nm-wavelength lithography. With more aggressive halo, the IBM team said it has produced the smallest working MOSFETs reported to date, with 4nm silicon body and 6nm gate lengths. IBM said its result suggests that aggressive thinning of the SOI layer is a promising option to drive CMOS device scaling.

IBM will present details of this research breakthrough in a paper entitled Extreme Scaling with Ultra-thin Silicon Channel MOSFETs at the International Electron Devices Meeting (IEDM) being held this week in San Francisco.